In recent years, FPGAs whose internal logic circuits are freely programmable have come into wide use. A device equipped with an FPGA incorporates an FPGA configuration circuit which is used to configure the FPGA by loading configuration data stored in a designated memory into the FPGA during power-up, etc. Some of such FPGA-equipped devices are designed to be able to configure the FPGA not only by using the configuration data stored in memory, but also by using an externally connected configuration data writer (hereinafter referred to as the “data writer”).
FIG. 1 is a block diagram schematically showing the configuration of an electronic device that can configure a built-in FPGA by using an externally connected data writer. The electronic device 1 includes an FPGA 2, an FPGA configuration device 3, and a memory 4. The FPGA configuration device 3 can configure the FPGA 2 by loading the configuration data stored in the memory 4 into the FPGA 2 during power-up of the electronic device 1, etc. Further, the electronic device 1 is configured so that the FPGA 2 can also be configured using the externally connected data writer 100.
When configuring the FPGA 2 from the data writer 100, the FPGA configuration device 3 stores the configuration data, which the data writer 100 writes to the FPGA 2, as new configuration data into the memory 4 in parallel with the configuration of the FPGA 2. For example, when power is turned on the next time, the FPGA configuration device 3 configures the FPGA 2 by using the newly stored configuration data.
Japanese Laid-open Patent Publication No. 2007-251329 discloses a circuit having a configurable core, a configuration data storage memory, a configuration controller, and a memory controller. Japanese Laid-open Patent Publication No. 8-76974 discloses a technique that stores configuration data in an internal configuration RAM and that downloads the configuration data from the RAM into an FPGA. Japanese Laid-open Patent Publication No. 2003-44303 discloses a technique that stores configuration data in a nonvolatile memory and that loads the configuration data from the nonvolatile memory into an FPGA.
When configuring the FPGA 2 by the data writer 100 externally connected to the electronic device 1, it is required that the data writing speed at which the FPGA configuration device 3 transfers the data to the memory 4 be faster than the data transfer speed at which the data writer 100 transfers the data to the FPGA 2. Accordingly, the configuration of the FPGA configuration device 3 and the device to be used as the memory 4 are chosen so as to satisfy the above requirement, which imposes constraints on the circuit design of the electronic device 1.